# Evolutionary Optimization Techniques in Analog Integrated Circuit Designs

### Abstract

The proposed genetic algorithm (GA) and particle swarm optimization (PSO) applied for the optimal design of a one-stage operational amplifier circuit with a current mirror load are studied in this work. The sizes of transistors are optimized using the proposed GA and PSO for improved areas and performance parameters of the circuit. A number of performance parameters are collected from the data set created by GA and PSO to optimize the size of transistors and other design parameters. The Spectre simulator is chosen for the simulation of circuit parameters to obtain necessary for the GA and PSO algorithm. Post-optimization results justify that the proposed GA and PSO methods are competitive with differential evolution regarding convergence speed, design specifications, and the optimal CMOS one-stage operational amplifier circuit parameters.

### References

Afacan, E., Lourenc¸o, N., Martins, R., and Dundar, G. Review: Machine learning techniques in analog/rf integrated circuit design, synthesis, layout, and test. Integration 77 (2021), 113–130.

Ahmed, R., Mahadzir, S., Rozali, N. E. M., Biswas, K., Matovu, F., and Ahmed, K. Artificial intelligence techniques in refrigeration system modelling and optimization: A multidisciplinary review. Sustainable Energy Technologies and Assessments 47 (2021), 101488.

Alawieh, M., Wang, F., and Li, X. Efficient hierarchical performance modeling for integrated circuits via bayesian colearning. In Proceedings of the 54th Annu. Design Automat. Conf. (2017), p. 1–6.

Alawieh, M. B., Wang, F., and Li, X. Efficient hierarchical performance modeling for analog and mixed-signal circuits via bayesian colearning. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 37 (2018), 2986–2998.

Alawieh, M. B., Williamson, S. A., and Pan, D. Z. Rethinking sparsity in performance modeling for analog and mixed circuits using spike and slab models. In Proceedings of the 56th Annu. Design Automat. Conf. (DAC) (2019), p. 1–6.

Alpaydin, G., Balkir, S., and Dundar, G. An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans. Evol. Comput. 7 (2003), 240–252.

Bishop, C. M., Ed. Pattern Recognition and Machine Learning. 2006.

Bujok, P., Lacko, M., and Kolenovsk´y, P. Differential evolution and engineering problems. MENDEL 29 (2023), 45–54.

Casella, G., and George, E. I. Explaining the gibbs sampler. Amer. Statistician 46 (1992), 167–174.

Chang, E., et al. Bag2: A process-portable framework for generatorbased ams circuit design. In Proceedings of the IEEE Custom Integr. Circuits Conf. (CICC) (2018), p. 1–8.

Cortes, C., Mohri, M., and Rostamizadeh, A. L2 regularization for learning kernels. In Proceedings of the Twenty-Fifth Conference on Uncertainty in Artificial Intelligence (UAI2009) (2012).

Gardner, J. R., Kusner, M. J., Xu, Z. E., Weinberger, K. Q., and Cunningham, J. P. Bayesian optimization with inequality constraints. In Proceedings of the ICML (2014), p. 937–945.

Glover, F. Tabu search — part ii. ORSA J. Comput. 2 (1990), 4–32.

Hakhamaneshi, K., Werblun, N., Abbeel, P., and c, V. S. Analog circuit generator based on deep neural network enhanced combinatorial optimization. In Proceedings of the 56th Annu. Design Automat. Conf. (2019), p. 1–2.

Hoang, T., Pham, H. X., and Tran, Q. H. A novel design of low-power, high-speed ota in 50nm-cmos technology. In 3rd Solid State Systems Symposium – VLSIs and Semiconductor Related Technologies (2014).

Hoerl, A. E., and Kennard, R. W. Ridge regression: Biased estimation for nonorthogonal problems. Technometrics 42 (2000), 80–86.

Ishwaran, H., and Rao, J. S. Spike and slab variable selection: Frequentist and bayesian strategies. Ann. Statist 33 (2005), 730–773.

Islamoglu, G., Cakici, T. O., Afacan, E., and Dundar, G. Artificial neural network assisted analog ic sizing tool. In Proceedings of the 16th Int. Conf. Synth., Modeling, Anal. Simulation Methods Appl. Circuit Design (SMACD) (2019), p. 9–12.

Jiao, F., and Doboli, A. A low-voltage, lowpower amplifier created by reasoning-based, systematic topology synthesis. In Proceedings of IEEE Int. Symp. Circuits Syst. (ISCAS) (2015), p. 2648–2651.

Kaveh, A., Ed. Advances in metaheuristic algorithms for optimal design of structures. 2014.

Kosari, A., Moosavifar, M., and Wentzloff, D. D. A 152 μw -99 dbm bpsk16-qam ofdm receiver for lpwan applications. In Proceedings of the IEEE Asian Solid-State Circuits Conf. (A-SSCC) (2018), p. 303–306.

Li, X., Zhang, W., and Wang, F. Large-scale statistical performance modeling of analog and mixed-signal circuits. In Proceedings of the IEEE Custom Integr. Circuits Conf. (2012), p. 1–8.

Li, Y., Wang, Y., Li, Y., Zhou, R., and Lin, Z. An artificial neural network assisted optimization system for analog design space exploration. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 39 (2020), 2640–2653.

Liashchynskyi, P. B., and Liashchynskyi, P. Grid search, random search, genetic algorithm: A big comparison for nas. ArXiv abs/1912.06059 (2019).

Lin, M. P.-H., Chang, Y.-W., and Hung, C.- M. Recent research development and new challenges in analog layout synthesis. In Proceedings of the 21st Asia South Pacific Design Automat. Conf. (ASP-DAC) (2016), p. 617–622.

Liu, B., Fernandez, F. V., and Gielen, G. G. E. Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE Trans. Comput.- Aided Design Integr. Circuits Syst. 30 (2011), 793–805.

Liu, B., Zhao, D., Reynaert, P., and Gielen, G. G. E. Gaspad: A general and efficient mm-wave integrated circuit synthesis method based on surrogate model assisted evolutionary algorithm. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 33 (2014), 169–182.

Liua, B., and Nikolaeva, A. Efficient global optimization of mems based on surrogate model assisted evolutionary algorithm. In Proceedings of the Design, Automat. Test Eur. Conf. Exhib. (DATE) (2016), pp. 555–558.

Lourenco, N., et al. On the exploration of promising analog ic designs via artificial neural networks. In Proceedings of the 15th Int. Conf. Synth., Modeling, Anal. Simulation Methods Appl. Circuit Design (SMACD) (2018), p. 133–136.

Lyu, W., et al. An efficient bayesian optimization approach for automated optimization of analog circuits. IEEE Trans. Circuits Syst. I, Reg. Papers 65 (2018), 1954–1967.

Lyu, W., Yang, F., Yan, C., Zhou, D., and Zeng, X. Batch bayesian optimization via multiobjective acquisition ensemble for automated analog circuit design. In Proceedings of the Int. Conf. Mach. Learn. (2018), p. 3306–3314.

Mallick, and Soumen. Optimal sizing of cmos analog circuits using gravitational search algorithm with particle swarm optimization. International Journal of Machine Learning and Cybernetics 8 (2017), 309–331.

Marler, R. T., and Arora, J. S. Survey of multi-objective optimization methods for engineering. Struct. Multidisciplinary Optim. 26 (2004), 369–395.

McConaghy, T. High-dimensional statistical modeling and analysis of custom integrated circuits. In Proceedings of the IEEE Custom Integr. Circuits Conf. (CICC) (2011), p. 1–8.

Meng, K.-H., Pan, P.-C., and Chen, H.-M. Integrated hierarchical synthesis of analog/rf circuits with accurate performance mapping. In Proceedings of the 12th Int. Symp. Qual. Electron. Design (2011), pp. 1–8.

Muteba, M. Optimization of air gap length and capacitive auxiliary winding in three-phase induction motors based on a genetic algorithm. Energies 14 (2021), 4407.

Naumowicz, M., Melosik, M., and Katarzy’nski, P. Technology migration of analogue cmos circuits using hooke-jeeves algorithm and genetic algorithms in multi-core cpu systems. In Proceedings of the 20th Int. Conf. Mixed Design Integr. Circuits Syst. (MIXDES) (2013), p. 267–272.

Nguyen, H. M., Pham, L. D., and Hoang, T. A novel li-ion battery charger using multi-mode ldo configuration based on 350 nm hv-cmos. Analog Integr Circ Sig Process 88 (2016), 505–516.

Nguyen, H. T., and Hoang, T. A novel framework of genetic algorithm and spectre to optimize delay and power consumption in designing dynamic comparators. Electronics 12 (2023), 3392.

Nocedal, J., and Wright, S., Eds. Numerical Optimization. 2006.

Okobiah, O., Mohanty, S., and Kougianos, E. Fast design optimization through simple kriging metamodeling: A sense amplifier case study. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22 (2014), 932–937.

Okobiah, O., Mohanty, S. P., and Kougianos, E. Exploring kriging for fast and accurate design optimization of nanoscale analog circuits. In Proceedings of the IEEE Comput. Soc. Annu. Symp. VLSI (2014), p. 244–247.

Pan, P.-C., Chen, H.-M., and Lin, C.-C. Page: Parallel agile genetic exploration towards utmost performance for analog circuit design. In Proceedings of the Design, Automat. Test Eur. Conf. Exhib. (DATE) (2013), p. 1849–1854.

Pan, P.-C., Huang, C.-C., and Chen, H.-M. An efficient learning-based approach for performance exploration on analog and rf circuit synthesis. In Proceedings of the 56th Annu. Design Automat. Conf. (2019), pp. 1–2.

Park, S. J., Bae, B., Kim, J., and Swaminathan, M. Application of machine learning for optimization of 3-d integrated circuits and systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017), 1856–1865.

Peng, B., Yang, F., Yan, C., Zeng, X., and Zhou, D. Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. In Proceedings of the Design, Automat. Test Eur. Conf. Exhib. (DATE) (2016), p. 1417–1422.

Qian, L., Bi, Z., Zhou, D., and Zeng, X. Automated technology migration methodology for a mixed-signal circuit based on multistart optimization framework. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015), 2595–2605.

Rojec, Z., Fajfar, I., and Burmen, A. Evolutionary synthesis of failure-resilient analog circuits. Mathematics 10 (2022), 156.

Shah, A., and Ghahramani, Z. Parallel predictive entropy search for batch global optimization of expensive objective functions. In Proceedings of the Adv. Neural Inf. Process. Syst. (2015), p. 3330–3338.

Shahriari, B., Swersky, K., Wang, Z., Adams, R. P., and de Freitas, N. Taking the human out of the loop: A review of bayesian optimization. In Proceedings of the IEEE (2016), p. 148–175.

Singhee, A., Singhal, S., and Rutenbar, R. A. Practical, fast monte carlo statistical static timing analysis: Why and how. In Proceedings of the IEEE/ACM Int. Conf. Computer-Aided Design (2008), p. 190–195.

Snoek, J., et al. Scalable bayesian optimization using deep neural networks. In Proceedings of the Int. Conf. Mach. Learn. (2015), p. 2171–2180.

Valencia-Ponce, M. A., Tlelo-Cuautle, E., and de la Fraga, L. G. On the sizing of cmos operational amplifiers by applying many-objective optimization algorithms. Electronics 10 (2021), 3148.

Vural, R. A., and Yildirim, T. Analog circuit sizing via swarm intelligence. AEU-International journal of electronics and communications 66 (2012), 732–740.

Wang, D., Tan, D., and Liu, L. Particle swarm optimization algorithm: an overview. Soft computing 22 (2018), 387–408.

Wang, F., et al. Bayesian model fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 35 (2016), 1255–1268.

Wang, H., Yang, J., Lee, H.-S., and Han, S., Eds. Learning to design circuits. 2018.

Wang, M., et al. Efficient yield optimization for analog and sram circuits via gaussian process regression and adaptive yield estimation. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 37 (2018), 1929–1942.

Wang, Y., Orshansky, M., and Caramanis, C. Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization. In Proceedings of the 51st ACM/EDAC/IEEE Design Automat. Conf. (DAC) (2014), pp. 1–6.

Wang, Z., Lee, K. H., and Verma, N. Overcoming computational errors in sensing platforms through embedded machine-learning kernels. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015), 1459–1470.

Williams, C. K., and Rasmussen, C. E., Eds. Gaussian Processes for Machine Learning, vol. 2. 2006.

Wu, J., and Frazier, P. The parallel knowledge gradient method for batch bayesian optimization. In Proceedings of the Adv. Neural Inf. Process. Syst. (2016), p. 3126–3134.

Yang, Y., et al. Smart-msp: A self-adaptive multiple starting point optimization approach for analog circuit synthesis. IEEE Trans. Comput.- Aided Design Integr. Circuits Syst. 37 (2018), 531–544.

Yu, S., Krishnapuram, B., Steck, H., Rao, R. B., and Rosales, R. Bayesian co-training. In Proceedings of the Adv. Neural Inf. Process. Syst. (2008), p. 1665–1672.

*MENDEL*. 29, 2 (Dec. 2023), 245-254. DOI:https://doi.org/10.13164/mendel.2023.2.245.

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